Magnetic memory read circuit and calibration method therefor

ABSTRACT

The present invention is directed to a nonvolatile memory device that includes one or more memory sectors and a read circuit for sensing the resistance state of a magnetic memory cell in the memory sectors. The read circuit includes first and second input nodes; a sense amplifier having first and second input terminals; a reference resistor connected to the first input node at one end and the first input terminal at the other end; a multiplexer having a first input, a second input, and an output, with the first input being connected to the second input node and the output being connected to the second input terminal; a first target resistor and an offset resistor connected in series between the second input node and the second input; and first and second current sources connected to the first and second input terminals, respectively.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a continuation of application Ser. No.17/031,542, filed on Sep. 24, 2020, which claims priority to provisionalapplication No. 63/073,370, filed on Sep. 1, 2020.

BACKGROUND

The present invention relates to a nonvolatile memory, and moreparticularly, to embodiments of sensing circuitry for the nonvolatilememory and method for using the same.

A resistance-switching memory device normally comprises an array ofmemory cells, each of which includes a memory element and a selectionelement, such as access transistor, coupled in series between twoelectrodes. The selection element functions like a switch to directcurrent or voltage through the selected memory element coupled thereto.Upon application of an appropriate voltage or current to the selectedmemory element, the resistance of the memory element would changeaccordingly, thereby switching the stored logic in the respective memorycell.

FIG. 1 is a schematic circuit diagram for a conventional memory array20, which comprises a plurality of memory cells 22 arranged in rows andcolumns with each of the memory cells 22 including an access transistor24 coupled to a resistance-switching memory element 26; a plurality ofparallel word lines 28 with each being coupled to the gates of arespective row of the access transistors 24 in a first direction; aplurality of parallel bit lines 30 with each being coupled to arespective column of the memory elements 26 in a second directionsubstantially perpendicular to the first direction; and a plurality ofparallel source lines 32 with each being coupled to a respective row orcolumn of the access transistors 24 in the first or second direction.

The resistance-switching memory element 26 may be classified into atleast one of several known groups based on their resistance-switchingmechanisms. The memory element of Phase Change Random Access Memory(PCRAM) may comprise a phase change chalcogenide compound, which canswitch between a resistive phase (amorphous or crystalline) and aconductive crystalline phase. The memory element of Conductive BridgingRandom Access Memory (CBRAM) relies on the statistical bridging ofmetal-rich precipitates therein for its switching mechanism. The memoryelement of CBRAM normally comprises a nominally insulating metal oxidematerial, which can switch to a lower electrical resistance state as themetal rich precipitates grow and link to form conductive paths orfilaments upon application of an appropriate voltage.

The memory element of Magnetic Random Access Memory (MRAM) normallyincludes a magnetic reference layer and a magnetic free layer with anelectron tunnel junction layer interposed therebetween. The magneticreference layer, the electron tunnel junction layer, and the magneticfree layer collectively form a magnetic tunnel junction (MTJ). Upon theapplication of an appropriate current to the MTJ, the magnetizationdirection of the magnetic free layer can be switched between twoconfigurations: parallel (i.e., same direction) and antiparallel (i.e.,opposite direction) with respect to the magnetization direction of themagnetic reference layer. The electron tunnel junction layer is normallymade of an insulating material with a thickness ranging from a few to afew tens of angstroms. When the magnetization directions of the magneticfree and reference layers are substantially parallel or oriented in asame direction, electrons polarized by the magnetic reference layer cantunnel through the insulating tunnel junction layer, thereby decreasingthe electrical resistance of the MTJ. Conversely, the electricalresistance of the MTJ is high when the magnetization directions of themagnetic reference and free layers are substantially anti-parallel ororiented in opposite directions. The stored logic in the magnetic memoryelement can be switched by changing the magnetization direction of themagnetic free layer between parallel and antiparallel configurationswith respect to the magnetization direction of the reference layer.Therefore, the two stable resistance states enable the MTJ to serve as anonvolatile memory element.

MRAM devices have almost unlimited read/write endurance but relativelysmaller sensing margin compared with other types of resistance-switchingmemory devices, such as phase change random access memory (PCRAM) andresistive random access memory (ReRAM). The resistance ratio ofhigh-to-low resistance state of MRAM is about 2-3, compared with 10²-10⁵for PCRAM and ReRAM.

FIG. 2 is a plot showing the resistance distributions 40 and 42respectively corresponding to the low and high resistance states of anMTJ population. The x-axis represents the electrical resistance whilethey-axis represents the number of MTJs having a particular electricalresistance. An MTJ having a resistance that falls within the R_(L)distribution 40 is considered to be in the low resistance (R_(L)) state.Likewise, an MTJ having a resistance that falls within the R_(H)distribution 42 is considered to be in the high resistance (R_(H))state. The resistance state of the MTJ may be determined during a readoperation by comparing the resistance of the MTJ with a referenceresistance (R_(REF)) that is somewhere in between the R_(L) distribution40 and the R_(H) distribution 42. One way to establish R_(REF) is tosimply take the average of the mean of R_(L) distribution and the meanof R_(H) distribution as shown in the plot. While being relativelysimple, this method results in reduced sensing margin for the highresistance state because of the inherently broader distribution thereof.Another way to select R_(REF) is to choose the midpoint in the gapbetween the R_(L) and R_(H) distributions 40 and 42 (e.g., the averageof R_(L) mean+3σ and R_(H) mean-3σ) as shown. Compared with the formermethod, the latter method improves the sensing margin for the highresistance state at room temperature, but suffers the same problem atelevated temperatures as the resistance of MTJ decreases.

For the foregoing reasons, there is a need for a circuit and a methodfor improving the sensing margin of MRAM.

SUMMARY

The present invention is directed to a nonvolatile memory devicecomprising a plurality of memory slices, each memory slice including oneor more memory sectors and a read circuit for sensing the resistancestate of a magnetic memory cell in the one or more memory sectors. Theread circuit comprises a first input node through which a referencecurrent passes; a second input node through which a read current and acalibration current from the one or more memory sectors pass; a senseamplifier having first and second input terminals; a first targetresistor and a balancing resistor connected in series between the firstinput node and the first input terminal of the sense amplifier; a firstcurrent source connected to the first input terminal of the senseamplifier at one end and ground at the other end; a multiplexer having afirst input terminal, a second input terminal, and an output terminal,with the first input terminal of the multiplexer being connected to thesecond input node and having the substantially same potential as thesecond input node and the output terminal of the multiplexer beingconnected to the second input terminal of the sense amplifier; a secondtarget resistor and an offset resistor connected in series between thesecond input node and the second input terminal of the multiplexer; anda second current source connected to the output terminal of themultiplexer at one end and ground at the other end. The first and secondtarget resistors are variable resistors and have the substantially sameresistance value.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features, aspects, and advantages of the presentinvention will become better understood with regard to the followingdescription, appended claims, and accompanying drawings where:

FIG. 1 is a schematic circuit diagram for an array of memory cells witheach memory cell including a resistance-switching memory element and anaccess transistor coupled in series between a bit line and a sourceline;

FIG. 2 is a plot showing low and high resistance distributions for asample population of magnetic tunnel junctions (MTJs);

FIG. 3 is a block diagram illustrating components of a memory device inaccordance with an exemplary embodiment of the present invention;

FIG. 4 is a diagram illustrating an example of the read and referencecurrent paths for the memory device of FIG. 3 in a read operation;

FIG. 5 is a schematic circuit diagram for a memory section and a readcircuit of the memory device of FIG. 3 ;

FIG. 6 is a schematic circuit diagram for an exemplary variableresistance circuit used for the first and second target resistors in theread circuit shown in FIG. 5 ;

FIG. 7 is a flow diagram illustrating an exemplary calibration processfor the read circuit involving the first target resistor having thecircuit configuration of FIG. 6 ;

FIG. 8 is a schematic circuit diagram for another exemplary variableresistance circuit used for the first and second target resistors in theread circuit shown in FIG. 5 ;

FIG. 9 is a block diagram illustrating components of a memory device inaccordance with another exemplary embodiment of the present invention;

FIG. 10 is a diagram illustrating an example of the read and referencecurrent paths for the memory device of FIG. 9 in a read operation; and

FIG. 11 is a schematic circuit diagram for a memory section and a readcircuit of the memory device of FIG. 9 .

For purposes of clarity and brevity, like elements and components willbear the same designations and numbering throughout the Figures, whichare not necessarily drawn to scale.

DETAILED DESCRIPTION

In the Summary above and in the Detailed Description, and the claimsbelow, and in the accompanying drawings, reference is made to particularfeatures (including method steps) of the invention. It is to beunderstood that the disclosure of the invention in this specificationincludes all possible combinations of such particular features. Forexample, where a particular feature is disclosed in the context of aparticular aspect or embodiment of the invention, or a particular claim,that feature can also be used, to the extent possible, in combinationwith and/or in the context of other particular aspects and embodimentsof the invention, and in the invention generally.

Where reference is made herein to a method comprising two or moredefined steps, the defined steps can be carried out in any order orsimultaneously, except where the context excludes that possibility, andthe method can include one or more other steps which are carried outbefore any of the defined steps, between two of the defined steps, orafter all the defined steps, except where the context excludes thatpossibility.

The term “at least” followed by a number is used herein to denote thestart of a range beginning with that number, which may be a range havingan upper limit or no upper limit, depending on the variable beingdefined. For example, “at least 1” means 1 or more than 1. The term “atmost” followed by a number is used herein to denote the end of a rangeending with that number, which may be a range having 1 or 0 as its lowerlimit, or a range having no lower limit, depending upon the variablebeing defined. For example, “at most 4” means 4 or less than 4, and “atmost 40%” means 40% or less than 40%. When, in this specification, arange is given as “a first number to a second number” or “a firstnumber-a second number,” this means a range whose lower limit is thefirst number and whose upper limit is the second number. For example,“25 to 100 nm” means a range whose lower limit is 25 nm and whose upperlimit is 100 nm.

Directional terms, such as “front,” “back,” “top,” “bottom,” and thelike, may be used with reference to the orientation of the illustratedfigure. Spatially relative terms, such as “beneath,” “below,” “under,”“lower,” “upper,” “above,” etc., may be used herein to describe oneelement's relationship to another element(s) as illustrated in thefigure. Since articles and elements can be positioned in a number ofdifferent orientations, these terms are intended for illustrationpurposes and in no way limit the invention, except where the contextexcludes that possibility.

FIG. 3 is a block diagram illustrating components of a memory device 100in accordance with an exemplary embodiment of the present invention. Thememory device 100 includes a plurality of I/O or memory slicesrepresented by memory slices 102A-102C. Each of the memory slices102A-102C has independent input/output from other slices and may includeone or two memory sectors. Each memory slice (e.g., 102A) may include afirst memory sector (e.g., 103A) and a read circuit (e.g., 112A)connected thereto. The first memory sector 103A includes a first memoryarray 104A, a first row decoder 106A for selecting one of word lines(WLs) traversing the first memory array 104A along a first direction, afirst column decoder 108A for selecting a bit line (BL) traversing thefirst memory array 104A along a second direction substantiallyperpendicular to the first direction, and a second column decoder 110Afor selecting a source line (not shown) traversing the memory array 104Aalong the second direction. The read circuit 112A is connected to theoutput of the first column decoder 108A.

The first memory array 104A is analogous to the memory array 20 shown inFIG. 1 and includes a plurality of memory cells arranged in rows andcolumns (not shown), a plurality of parallel word lines (WLs), aplurality of parallel bit lines (BLs), and a plurality of parallelsource lines (not shown). The first memory array 104A may also include areference bit line (RBL) connected to the read circuit 112A through afirst switch 114A. The reference bit line (RBL) may provide a referencesignal or current to the read circuit 112A when determining theresistance state of a memory cell in the memory array 104A.

Each memory slice (e.g., 102A) may further include a second memorysector (e.g., 115A) connected to the read circuit (e.g., 112A). Thesecond memory sector 115A includes a second memory array 124A, a secondrow decoder 126A for selecting a word line (WL) traversing the secondmemory array 124A along the first direction, a third column decoder 128Afor selecting a bit line (BL) traversing the second memory array 124Aalong the second direction substantially perpendicular to the firstdirection, and a fourth column decoder 130A for selecting a source line(not shown) traversing the memory array 124A along the second direction.The second memory array 124A may also include a reference bit line (RBL)connected to the read circuit 112A through a second switch 134A. Thefirst and second memory sectors 103A and 115A may be physically arrangedin a mirror-image geometry on opposite sides of the read circuit 112Athat acts as the mirror line.

Since each of the memory slices 102A-102C includes a respective one ofthe read circuits 112A-112C, a memory cell from each of the memoryslices 102A-102C may be independently sensed at the same time. Forexample and without limitation, FIG. 4 shows that a memory cell from thefirst memory sector 103A of the first memory slice 102A, another memorycell from the second memory sector 115B of the second memory slice 102B,and still another memory cell from the first memory sector 103C of thelast memory slice 102C are simultaneously sensed. During the sensing orread operation, the read current, I_(READ), passes through the memorycell selected for the read operation, the bit line connected thereto,and reaches the read circuit via the first or third column decoder,while the reference current (I_(REF)) passes through the reference bitline (RBL) to reach the read circuit via the first or second switch.

FIG. 5 is schematic circuit diagram showing the first memory sector 103Aand the read circuit 112A of the first memory slice 102A. The firstmemory sector 103A includes the first memory array 104A, the first rowdecoder 106A, the first and second column decoders 108A and 110A, andthe first switch 114A. The first memory array 104A includes a pluralityof memory cells arranged in rows and columns as represented by cells140A-140I, a plurality of word lines represented by lines 146A-146C, aplurality of bit lines represented by lines 148A-148C, and a pluralityof source lines represented by lines 150A-150C. Each memory cell (e.g.,140C) includes a resistance-switching memory element (e.g., 142C) and anaccess transistor (e.g., 144C) coupled in series between a respectiveone of the bit lines (e.g., 148C) and a respective one of the sourcelines (e.g., 150C). Each of the plurality of word lines 146A-146C iscoupled to the gates of a respective row of the access transistors in afirst direction. Each of the plurality of bit lines 148A-148C is coupledto a respective column of the memory cells 140A-140I at one end thereof(e.g., memory element) along a second direction. Each of the pluralityof source lines 150A-150C is coupled to a respective column of thememory cells 140A-140I at the other end thereof (e.g., accesstransistor) along the second direction. The first and second directionsmay be substantially orthogonal to each other. The positions of theresistance-switching memory element (e.g., 142C) and the accesstransistor (e.g., 144C) in a memory cell (e.g., 140C) may be swappedsuch that the memory element (e.g., 142C) and the access transistor(e.g., 144C) are disposed adjacent to the source line (e.g., 150C) andthe bit line (e.g., 148C), respectively.

Each of the resistance-switching memory elements (e.g., 142C) may changethe resistance state thereof by any suitable switching mechanism, suchas but not limited to phase change, precipitate bridging,magnetoresistive switching, or any combination thereof. In oneembodiment, the memory element 142C comprises a phase changechalcogenide compound, such as but not limited to Ge₂Sb₂Te₅ or AgInSbTe,which can switch between a resistive phase and a conductive phase. Inanother embodiment, the memory element 142C comprises a nominallyinsulating metal oxide material, such as but not limited to NiO, TiO₂,or Sr(Zr)TiO₃, which can switch to a lower electrical resistance stateas metal rich precipitates grow and link to form conductive paths uponapplication of an appropriate voltage. In still another embodiment, thememory element 142C comprises a magnetic free layer, a magneticreference layer, and an insulating electron tunnel junction layerinterposed therebetween, which collectively form a magnetic tunneljunction (MTJ). When a switching current is directly applied to the MTJ,the magnetic free layer would switch the magnetization directionthereof, thereby changing the electrical resistance of the MTJ. Themagnetic free layer may have a variable magnetization directionsubstantially perpendicular to a layer plane thereof. The magneticreference layer may have a fixed magnetization direction substantiallyperpendicular to a layer plane thereof. Alternatively, the magnetizationdirections of the magnetic free and reference layers may be orientedparallel to the respective layer planes.

The first memory array 104A further includes a column of accesstransistors 144J-144L with the gate of each access transistor coupled toa respective one of the word lines 146A-146C. The column of accesstransistors 144J-144L, which are used to control the reference currentduring sensing, can be regarded as “dummy” cells without memoryelements. The column of access transistors 144J-144L are coupled to areference bit line 152A at one of the source and drain and to areference source line 154A at the other one of the source and drain. Thefirst memory array 104A may further include one or more rows of accesstransistors 144M-144T connected to one or more word lines 146D and 146Eat the gates thereof. Each transistor of the rows of the accesstransistors 144M-144T is connected to a respective one of the bit lines148A-148C or the reference bit line 152A at one of the source and drainand to a respective one of the source lines 150A-150C or the referencesource line 154A at the other one of the source and drain.

All of the word lines 146A-146E may be connected to the row decoder106A, which allows one the word line 146A-146E to be selected for reador write operation. A voltage (V_(Y1)) may be applied to one of thesource lines 150A-150C via the second column decoder 110A connectedthereto during the read or write operation. Similarly, another voltage(e.g., V_(Y2)) may be applied to the reference source line 154A througha third switch 156A. In an embodiment, the voltages V_(Y1) and V_(Y2)are set to the same voltage (V_(READ)) during the read operation and thecalibration of the read circuit 112A. The first column decoder 108Aconnected to the bit lines 148A-148C allows one of the bit lines148A-148C to be connected to Node B of the read circuit 112A. Likewise,the reference bit line 152A may be connected to Node A of the readcircuit 112A via the first switch 114A.

The read circuit 112A includes two input terminals at Nodes A and B, afirst target resistor (R_(TARGET)) 160 and a balancing resistor(R_(BAL)) 162 connected in series between Nodes A and C, a first currentsource 164 connected to Node C at one end and ground at the other end, amultiplexer (MUX) 168 with one of the two inputs connected to Node B, asecond target resistor (R_(TARGET)) 170 and an optional offset resistor(R_(OFFSET)) 172 connected in series between Node B and the other one ofthe two inputs of the multiplexer (MUX) 168, whose output is connectedto Node D, a second current source 174 connected to Node D at one endand ground at the other end, and a sense amplifier 166 with one input(e.g., negative terminal) connected to Node C and the other input (e.g.,positive terminal) connected to Node D. The first and second targetresistors 160 and 170 are variable resistors having same designspecifications. However, the actual resistances of the resistors 160 and170 may be different owing to manufacturing variation. The balancingresistor (R_(BAL)) 162 and the optional offset resistor (R_(OFFSET)) 172may also be variable resistors.

During calibration of the read circuit 112A, the word line 146Dconnected to the row of transistors 144M-144P may be selected via therow decoder 106A to allow the reference current (I_(REF)) to flow fromthe reference source line 154A with the voltage V_(READ) appliedthereto, through the access transistor 144M, the reference bit line152A, and the first switch 144A, to the input terminal Node A of theread circuit 112A. From Node A, the reference current (I_(REF)) passesthrough the first target resistor (R_(TARGET)) 160, the balancingresistor (R_(BAL)) 162, and the first current source 164, and to ground.

The selection of the word line 146D during calibration also enables thecalibration current (I_(CAL)) to flow from one of the source lines150A-150C (e.g., 150C) selected through the second column decoder 110Aand having the applied voltage of V_(READ), through a respective one ofthe access transistors 144N-144P (e.g., 144P), a respective one of thebit lines 148A-148C (e.g., 148C), and the first column decoder 108A, tothe input terminal Node B of the read circuit 112A. From Node B, thecalibration current (I_(CAL)) flows through the second target resistor(R_(TARGET)) 170, the optional offset resistor (R_(OFFSET)) 172 ifpresent, the multiplexer (MUX) 168, the second current source 174, andto ground. The sense amplifier 166 measures the voltage differential atNodes C and D along the reference current path and the calibrationcurrent path, respectively. Neither the reference current (I_(REF)) northe calibration current (I_(CAL)) passes through any of the memory cells140A-140I containing the memory elements.

In the read operation, a memory cell (e.g., 140C) is selected forsensing by selecting the word line (e.g., 146A) connected thereto. Thesource line 150C connected to the selected memory cell 140C is selectedby the second column decoder 110A and may have a potential of V_(READ).The bit line 148C connected to the selected memory cell 140C is selectedby the first column decoder 108A, thereby allowing the read current(I_(READ)) to flow from the source line 150C, through the accesstransistor 144C, the memory element 142C, the bit line 148C, and thefirst column decoder 108A, to Node B of the read circuit 112A. From NodeB, the read current (I_(READ)) passes the multiplexer (MUX) 168, Node D,the second current source 174, and to ground, bypassing the secondtarget resistor (R_(TARGET)) 170 and the optional offset resistor(R_(OFFSET)) 172. The multiplexer (MUX) 168 is used to select differentcurrent paths during the read and calibration operations.

The selection of the word line 146A during the read operation andactivation of the first and third switches 114A and 156A allows thereference current (I_(REF)) to flow from the reference source line 154A,which may have a potential of V_(READ) applied thereto, through theaccess transistor 144J, the reference bit line 152A, and the firstswitch 114A, to Node A of the read circuit 112A. From Node A, thereference current (I_(REF)) passes through the first target resistor(R_(TARGET)) 160, the balancing resistor (R_(BAL)) 162, Node C, and thefirst current source 164, and to ground.

The sense amplifier 166 measures the voltage differential between NodesC and D along the reference current path and the read current path,respectively. The first target resistor (R_(TARGET)) 160 and thebalancing resistor (R_(BAL)) 162 collectively function as the referenceresistor, whose resistance is ideally somewhere in between the low andhigh resistances of the memory element 142C. When the memory element142C is in the low resistance state, the voltage drop across the memoryelement 142C may be less than the voltage drop across the first targetresistor (R_(TARGET)) 160 and the balancing resistor (R_(BAL)) 162,resulting in the voltage of Node D being higher than that of Node C.Conversely, the voltage drop across the memory element 142C may begreater than the voltage drop across the first target resistor(R_(TARGET)) 160 and the balancing resistor (R_(BAL)) 162 when thememory element 142C is in the high resistance state, resulting in thevoltage of Node D being lower than that of Node C.

Knowing the low and high resistance distributions 40 and 42corresponding to the memory elements of the memory array 104A as shownin FIG. 2 , the reference resistance (R_(REF)), which is collectivelyprovided by the first target resistor (R_(TARGET)) 160 and the balancingresistor (R_(BAL)) 162, may be simply set to a value somewhere inbetween the R_(L) distribution 40 and the R_(H) distribution 42 in anideal situation. However, the potential mismatch of the sense amplifier166 at the input terminals (i.e., Nodes C and D), which may be caused bythe differences between the read and reference current paths and thedeviation from design specifications of components caused bymanufacturing, including the sense amplifier 166 itself, can cause abias in the sensing process.

Accordingly, the read circuit 112A may be calibrated prior to usage tocorrect any potential sensing bias caused by the above cited factors.Calibration of the read circuit 112A will now be described withreference to FIG. 5 . The calibration process begins by setting theresistance of the first and second target resistors (R_(TARGET)) 160 and170 to an initial value (e.g., approximately middle of the resistancerange of R_(TARGET) or a value somewhere in between the R_(L) and R_(H)distributions) and setting the resistance of the balancing resistor(R_(BAL)) 162 to another value (e.g., minimum value or zero). Theresistance of the offset resistor (R_(OFFSET)) 172 is then set to avalue that renders the resistance of the calibration current path to behigher than that of the reference current path (i.e., Node D having alower potential than Node C). The offset resistor (R_(OFFSET)) 172 isneeded especially when the calibration current path has a lowerresistance than the reference current path.

When the reference current (I_(REF)) and the calibration current(I_(CAL)) initially flow through the read circuit 112A, one of theinputs (e.g., positive terminal) of the sense amplifier 166 connected toNode D will be at a lower potential than the other input (e.g., negativeterminal) connected to Node C because the calibration current pathinitially has a higher resistance, thereby causing the sense amplifier166 to output a signal (e.g., “0”). As the calibration process continuesby gradually increasing the resistance of the balancing resistor(R_(BAL)) 162 from its initial setting, the output of the senseamplifier 166 will eventually flip to the opposite signal (e.g., “1”)when the resistances of the reference and calibration current paths aresubstantially balanced. The resistance of the balancing resistor(R_(BAL)) 162 may therefore be fixed at or near the point where theoutput signal of the sense amplifier 166 flips.

After fixing the resistance of the balancing resistor (R_(BAL)) 162, thecalibration process may further proceed by adjusting the resistance ofthe first target resistor (R_(TARGET)) 160 such that the referenceresistance (R_(REF)) falls in between the R_(L) distribution 40 and theR_(H) distribution 42 as shown in FIG. 2 . FIG. 6 is a schematic circuitdiagram for the first target resistor (R_(TARGET)) 160 in accordancewith an embodiment of the present invention. The first target resistor(R_(TARGET)) 160 may include a variable resistance circuit 180 thatcomprises N+1 number of sub-circuits connected in series. Eachsub-circuit includes a transistor and a resistor with fixed resistanceconnected in parallel. The resistance of the resistor in the sub-circuitdoubles in the successive sub-circuit in the sequence the sub-circuits,such that the last sub-circuit in the series includes a resistor havinga resistance of 2^(N)R, where R represents the resistance of theresistor in the first sub-circuit of the sequence of sub-circuits andthe minimum incremental adjustment in the resistance of the variableresistance circuit 180. The resistance of the first target resistor(R_(TARGET)) 160 may be adjusted by N+1 input signals (i.e., Input <0>to Input <N>) to the transistors of the respective sub-circuits, whichcollectively provide a nominal resistance range of 0 to (2^(N+1)−1)R.The nominal resistance of the first target resistor (R_(TARGET)) 160becomes 0 and (2^(N+1)−1)R when all input signals (i.e., Input <0> toInput <N>) are set to “1” and “0”, respectively. During calibration ofthe balancing resistor (R_(BAL)) as described above, the resistance ofthe first and second target resistors (R_(TARGET)) 160 and 170 may beset to approximately half of their maximum by setting the last inputsignal (i.e., Input <N>) to “0” while setting the rest of the inputsignals (i.e., Input <0> to Input <N−1>) to “1”.

FIG. 7 is a flow diagram describing the calibration process for thefirst target resistor (R_(TARGET)) 160 having the circuit configurationshown in FIG. 6 . The process begins by setting the initial resistanceof the first target resistor (R_(TARGET)) 160 to approximately half ofthe maximum resistance (e.g., Input <N>=“0” and others set to “1”) andinitializing the loop counter (i.e., p=0) at step 200. After step 200,the input pointer (k), which is used to identify the input signal to thefirst target resistors (R_(TARGET)) 160, is set to equal to N−p at step202, where N corresponds to the last input signal (i.e., Input <N>) andmay be any integer greater than 2. After step 202, the process continuesto step 204, where a decision is made as to whether the pointer hasreached zero. If so, the calibration process for the first targetresistor (R_(TARGET)) 160 will be terminated. Otherwise, the processcontinues to step 206, where the resistance state of a population ofMTJs, half of which had been previously written to R_(H) and the otherhalf of which had been previously written to R_(L), is sensed usingI_(READ) and I_(REF) as described above. The number of MTJs in thepopulation can range from a few tens to the entire first memory array104A. During the read process, the sense amplifier 166 will output “1”when Node D, which is connected to the positive terminal of the senseamplifier 166, has a higher voltage than Node C, which is connected tothe negative terminal of the sense amplifier 166. Conversely, the senseamplifier 166 will output “0” when Node C has a higher voltage than NodeD. The numbers of “1” and “0” output from the sense amplifier 166 isrecorded by a counter. The loop is repeated until the input pointer, k,becomes zero. The calibration process for the balancing resistor(R_(BAL)) 162 and the first target resistor (R_(TARGET)) 160 asdescribed above may be repeated for all memory sectors within a memoryslice. Accordingly, the memory sectors within a memory slice may havedifferent R_(TARGET) resistance values.

Next, at step 208, where a decision is made as to whether the number of“0” output from the sense amplifier 166 is greater than the number of“1” output. If so, Input <k−1> of the variable transistor circuit 180shown in FIG. 6 is set to “0” at step 210. Otherwise, the processadvances to step 212, where Input <k> and Input <k−1> are set to “1” and“0”, respectively. After step 210 or 212, the loop counter p isincremented by 1 at step 214, after which the process loops back to step202 to decrement the input pointer k.

FIG. 8 is a schematic circuit diagram for the first target resistor(R_(TARGET)) 160 in accordance with another embodiment of the presentinvention. Compared with the embodiment of FIG. 6 , the first targetresistor (R_(TARGET)) 160 of FIG. 8 further includes a circuit 220connected to the variable resistance circuit 180 in series. The circuit220 includes multiple memory elements, such as MTJs, that act asresistors. For example and without limitation, the circuit 220 mayfurther include two sub-circuits connected in series. The firstsub-circuit may include two memory elements MJT1 222 and MTJ2 224connected in parallel. The second sub-circuit may include two othermemory elements MJT3 226 and MTJ4 228 connected in parallel. The use ofthe circuit 220 may allow more accurate targeting of the initial valueof the first target resistor (R_(TARGET)) 160 and the second targetresistor (R_(TARGET)) 170 with respect to the R_(L) and R_(H)distributions without a priori knowledge about the electrical propertiesof the MTJ. For example, if the initial value is desired to be at ornear the average of the R_(L) distribution, then all MTJs 222-228 may beset to R_(L). Conversely, if the initial value is desired to be at ornear the average of the R_(H) distribution, then all MTJs 222-228 may beset to R_(H). Setting one of the MTJs 222 and 224 in the firstsub-circuit to R_(L) and the other one to R_(H), and one of the MTJs 226and 228 in the second sub-circuit to R_(L) and the other one to R_(H)will result in the initial value being at or near the average of theR_(L) and R_(H) distributions. In an embodiment, all four MTJs 222-224are set to R_(L) and the variable resistance circuit 180 is set to aresistance value such that the resistance of the first and second targetresistors 160 and 170 falls in between the R_(L) and R_(H) distributionsduring calibration of the balancing resistor 162. Alternatively, theadjustment of the first target resistor 160 of FIG. 8 , if necessary,may be similarly carried out in accordance with the flow chart of FIG. 7with the exception that the initial resistance at step 200 is set by theMTJs 222-228 (e.g., all set to R_(L)) and all input signals to thevariable resistance circuit 180 may be set to “1”. The entirecalibration steps 200-214 illustrated in FIG. 7 may be repeated for allmemory sectors within a memory slice. Accordingly, the memory sectorswithin a memory slice may have different R_(TARGET) resistance values.

FIG. 9 is a block diagram illustrating components of a memory device 250in accordance with another exemplary embodiment of the presentinvention. The memory device 250 includes a plurality of I/O or memoryslices represented by memory slices 252A-252C. Each of the memory slices252A-252C has independent input/output from other slices and may includetwo or more memory sectors. Each memory slice (e.g., 252A) may include afirst plurality of memory sectors (e.g., 254A and 256A) connected to afirst plurality of global bit lines (GBLs), which may be furtherconnected to a read circuit (e.g., 112A) through a first column decoder(e.g., 258A). Each memory sector (e.g., 254A) includes a memory array(e.g., 260A), a row decoder (e.g., 262A) for selecting a word line (WL)traversing the memory array 260A along a first direction, a global bitline decoder (GBLD) (e.g., 264A) for connecting a local bit line (LBL)to a respective one of the first plurality of global bit lines (GBLs)traversing the first plurality of memory sectors 254A and 256A along asecond direction substantially perpendicular to the first direction, anda global source line decoder (GSLD) (e.g., 266A) for connecting a localsource line (not shown) to a respective one of a first plurality ofglobal source lines (not shown) traversing the first plurality of memorysectors 254A and 256A along the second direction.

The memory array 260A is analogous to the first memory array 104A shownin FIG. 5 and includes a plurality of memory cells arranged in rows andcolumns (not shown), a plurality of parallel word lines (WLs), aplurality of local bit lines (LBLs), and a plurality of local sourcelines (not shown). The memory array 260A may also include a localreference bit line (LRBL) connected to a first global reference bit line(GRBL) through the global bit line decoder (GBLD) 264A. The first globalreference bit line (GRBL) may be connected to the read circuit 112Athrough a first switch 268A. The first global reference bit line (GRBL)may provide a reference signal or current to the read circuit 112A whensensing the resistance state of a memory cell in the first plurality ofmemory sectors 254A and 256A. Other memory sectors in the firstplurality of memory sectors may be substantially identical to the memorysector 254A.

Each memory slice (e.g., 252A) may further include a second plurality ofmemory sectors (e.g., 270A and 272A) connected to a second plurality ofglobal bit lines (GBLs), which may be further connected to the readcircuit (e.g., 112A) through a second column decoder (e.g., 273A). Likethe first plurality of memory sectors 254A and 256A, each of the secondplurality of memory sectors (e.g., 270A) includes a memory array (e.g.,274A), a row decoder (e.g., 276A) for selecting a word line (WL)traversing the memory array 274A along a first direction, a global bitline decoder (GBLD) (e.g., 278A) for connecting a local bit line (LBL)to a respective one of a second plurality of global bit lines (GBLs)traversing the second plurality of memory sectors 270A and 272A along asecond direction substantially perpendicular to the first direction, anda global source line decoder (GSLD) (e.g., 280A) for connecting a localsource line (not shown) to a respective one of a second plurality ofglobal source lines (not shown) traversing the second plurality ofmemory sectors 270A and 272A along the second direction. The memorysector 270A may also include a local reference bit line (LRBL) connectedto a second global reference bit line (GRBL) through the global bit linedecoder (GBLD) 278A. The second global reference bit line (GRBL)traverses the second plurality of memory sectors 270A and 272A along thesecond direction and connects local reference bit lines of the secondplurality of memory sectors 270A and 272A to the read circuit 112A via asecond switch 282A. The second global reference bit line (GRBL) mayprovide a reference signal or current to the read circuit 112A whensensing the resistance state of a memory cell in the second plurality ofmemory sectors 270A and 272A. Other memory sectors in the secondplurality of memory sectors may be substantially identical to the memorysector 270A. Moreover, the first and second plurality of memory sectorsmay be physically arranged in a mirror-image geometry on opposite sidesof the read circuit 112A that acts as the mirror line.

Since each of the memory slices 252A-252C includes a respective one ofthe read circuits 112A-112C, a memory cell from each of the memoryslices 252A-252C may be independently sensed at the same time. Forexample and without limitation, FIG. 10 shows that a memory cell fromthe memory sector 256A of the first memory slice 252A, another memorycell from the memory sector 254B of the second memory slice 252B, andstill another memory cell from the memory sector 270C of the last memoryslice 252C are simultaneously sensed. During the sensing or readoperation, the read current, I_(READ), passes through the memory cellselected for the read operation, the local bit line (LBL) connected tothe selected memory cell, and the global bit line (GBL) connected to thelocal bit line (LBL), and reaches the read circuit via the first orsecond column decoder, while the reference current (I_(REF)) passesthrough the local reference bit line (LRBL) and the global reference bitline (GRBL) to reach the read circuit via the first or second switch.

FIG. 11 is schematic circuit diagram showing the memory sector 254A, thefirst column decoder 258A, the first switch 268A, and the read circuit112A of the first memory slice 252A. The memory sector 254A includes thememory array 260A, the row decoder 262A, the global bit line decoder(GBLD) 264A, the global source line decoder (GSLD) 266A. The memoryarray 260A includes a plurality of memory cells arranged in rows andcolumns as represented by cells 340A-340I, a plurality of word linesrepresented by lines 346A-346C, a plurality of local bit linesrepresented by lines 348A-348C, and a plurality of local source linesrepresented by lines 350A-350C. Each memory cell (e.g., 340C) includes aresistance-switching memory element (e.g., 342C) and an accesstransistor (e.g., 344C) coupled in series between a respective one ofthe local bit lines (e.g., 348C) and a respective one of the localsource lines (e.g., 350C). Each of the plurality of word lines 346A-346Cis coupled to the gates of a respective row of the access transistors ina first direction. Each of the plurality of local bit lines 348A-348C iscoupled to a respective column of the memory cells 340A-340I at one endthereof (e.g., memory element) along a second direction. Each of theplurality of local source lines 350A-350C is coupled to a respectivecolumn of the memory cells 340A-340I at the other end thereof (e.g.,access transistor) along the second direction. The first and seconddirections may be substantially orthogonal to each other. The positionsof the resistance-switching memory element (e.g., 342C) and the accesstransistor (e.g., 344C) in a memory cell (e.g., 340C) may be swappedsuch that the memory element (e.g., 342C) and the access transistor(e.g., 344C) are disposed adjacent to the local source line (e.g., 350C)and the local bit line (e.g., 348C), respectively. At the global bitline decoder (GBLD) 264A, each of the plurality of local bit lines348A-348C may be connected to a respective one of the first plurality ofglobal bit lines 351A-351C traversing the first plurality of memorysectors 254A and 256A along the second direction. The first plurality ofglobal bit lines 351A-351C may be connected to the read circuit 112A atNode B through the first column decoder 258A. At the global source linedecoder (GSLD) 266A, each of the plurality of local source lines350A-350C may be connected to a respective one of the first plurality ofglobal source lines (not shown) traversing the first plurality of memorysectors 254A and 256A along the second direction.

Each of the resistance-switching memory elements (e.g., 342C) may changethe resistance state thereof by any suitable switching mechanism, suchas but not limited to phase change, precipitate bridging,magnetoresistive switching, or any combination thereof. In oneembodiment, the memory element 342C comprises a phase changechalcogenide compound, such as but not limited to Ge₂Sb₂Te₅ or AgInSbTe,which can switch between a resistive phase and a conductive phase. Inanother embodiment, the memory element 342C comprises a nominallyinsulating metal oxide material, such as but not limited to NiO, TiO₂,or Sr(Zr)TiO₃, which can switch to a lower electrical resistance stateas metal rich precipitates grow and link to form conductive paths uponapplication of an appropriate voltage. In still another embodiment, thememory element 342C comprises a magnetic free layer, a magneticreference layer, and an insulating electron tunnel junction layerinterposed therebetween, which collectively form a magnetic tunneljunction (MTJ). When a switching current is directly applied to the MTJ,the magnetic free layer would switch the magnetization directionthereof, thereby changing the electrical resistance of the MTJ. Themagnetic free layer may have a variable magnetization directionsubstantially perpendicular to a layer plane thereof. The magneticreference layer may have a fixed magnetization direction substantiallyperpendicular to a layer plane thereof. Alternatively, the magnetizationdirections of the magnetic free and reference layers may be orientedparallel to the respective layer planes.

The memory array 260A further includes a column of access transistors344J-344L with the gate of each access transistor coupled to arespective one of the word lines 346A-346C. The column of accesstransistors 344J-344L, which are used to control the reference currentduring sensing, can be regarded as “dummy” cells without memoryelements. The column of access transistors 344J-344L are coupled to alocal reference bit line 352A at one of the source and drain and to alocal reference source line 354A at the other one of the source anddrain. The local reference bit line 352A may be connected to the firstglobal reference bit line 356A, which in turn may be connected to theread circuit 112A at Node A through the first switch 268A. The memoryarray 260A may further include one or more rows of access transistors344M-344T connected to one or more word lines 346D and 346E at the gatesthereof. Each transistor of the rows of the access transistors 344M-344Tis connected to a respective one of the local bit lines 348A-348C or thelocal reference bit line 352A at one of the source and drain and to arespective one of the local source lines 350A-350C or the localreference source line 354A at the other one of the source and drain.

All of the word lines 346A-346E may be connected to the row decoder262A, which allows one the word line 346A-346E to be selected for reador write operation. A voltage (V_(Y1)) may be applied to the localsource lines 350A-350C from the first plurality of global source lines(not shown) via the global source line decoder (GSLD) 266A during theread or write operation. Similarly, another voltage (e.g., V_(Y2)) maybe applied to the local reference source line 354A from the first globalreference source line (not shown) via the global source line decoder(GSLD) 266A. In an embodiment, the voltages V_(Y1) and V_(Y2) are set tothe same voltage (V_(READ)) during the read operation and calibration ofthe read circuit 112A. The first column decoder 258A connected to thefirst plurality of global bit lines 351A-351C allows one of the globalbit lines 351A-351C to be connected to Node B of the read circuit 112A.Likewise, the first global reference bit line 356A, which provides thereference signal in the read operation, may be connected to Node A ofthe read circuit 112A via the first switch 268A.

In a read operation, a read voltage (i.e., V_(READ)) is applied to aselected one of the first plurality of global source lines (not shown),causing a read current (I_(READ)) to flow from the selected globalsource line through the global source line decoder (GSLD) 266A, arespective one of the local source lines (e.g., 350C) connected to theselected global source line, a memory cell (e.g., 340C) connected to thelocal source line 350C and a selected word line (e.g., 346A), a localbit line (e.g., 348C) connected to the selected memory cell 340C, theglobal bit line decoder (GBLD) 264A, a respective one of the firstplurality of global bit lines (e.g., 351C), and the first column decoder258A, to Node B of the read circuit 112A. Meanwhile, a reference voltagethat is substantially identical to the read voltage (e.g., V_(READ)) maybe applied to the first global reference source line (not shown),thereby causing a reference current (I_(REF)) to flow from the firstglobal reference source line through the global source line decoder(GSLD) 266A, the local reference source line 354A, one of the column ofaccess transistors (e.g., 344J) connected to the selected word line346A, the local reference bit line 352A, the global bit line decoder(GBLD) 264A, the first global reference bit line 356A, and the firstswitch 268A, to Node A of the read circuit 112A. The reference current(I_(REF)) does not pass through any of the memory cells (340A-340I).

In a calibration operation, a calibration voltage (i.e., V_(READ)) isapplied to a selected one of the first plurality of global source lines(not shown), causing a calibration current (I_(CAL)) to flow from theselected global source line through the global source line decoder(GSLD) 266A, a respective one of the local source lines (e.g., 350C)connected to the selected global source line, an access transistor(e.g., 344P) of the rows of access transistors 344M-344T connected tothe selected local source line 350C and a selected word line (e.g.,346D), a local bit line (e.g., 348C) connected to the selected accesstransistor 344P, the global bit line decoder (GBLD) 264A, a respectiveone of the first plurality of global bit lines (e.g., 351C), and thefirst column decoder 258A, to Node B of the read circuit 112A.Meanwhile, a reference voltage that is substantially identical to thecalibration voltage (e.g., V_(READ)) may be applied to the first globalreference source line (not shown), thereby causing a reference current(I_(REF)) to flow from the first global reference source line throughthe global source line decoder (GSLD) 266A, the local reference sourceline 354A, an access transistor (e.g., 344M) of the rows of accesstransistors 344M-344T connected to the local reference source line 354Aand the selected word line 346D, the local reference bit line 352A, theglobal bit line decoder (GBLD) 264A, the first global reference bit line356A, and the first switch 268A, to Node A of the read circuit 112A.Neither the calibration current (I_(CAL)) nor the reference current(I_(REF)) passes through any of the memory cells (340A-340I).

With continuing reference to FIG. 11 , the read circuit 112A andoperation thereof are substantially identical to the read circuit 112Aand its operation shown in FIGS. 5-8 and described above.

While the present invention has been shown and described with referenceto certain preferred embodiments, it is to be understood that thoseskilled in the art will no doubt devise certain alterations andmodifications thereto which nevertheless include the true spirit andscope of the present invention. Thus the scope of the invention shouldbe determined by the appended claims and their legal equivalents, ratherthan by examples given.

Any element in a claim that does not explicitly state “means for”performing a specified function, or “step for” performing a specificfunction, is not to be interpreted as a “means” or “step” clause asspecified in 35 U.S.C. § 112, ¶6. In particular, the use of “step of” inthe claims herein is not intended to invoke the provisions of 35 U.S.C.§ 112, ¶6.

What is claimed is:
 1. A nonvolatile memory device comprising one ormore memory sectors and a read circuit for sensing a resistance state ofa magnetic memory cell in said one or more memory sectors, said readcircuit comprising: a first input node through which a reference currentpasses; a second input node through which a read current and acalibration current from said one or more memory sectors pass; a senseamplifier having first and second input terminals; a reference resistorconnected to said first input node at one end and said first inputterminal of said sense amplifier at the other end; a first currentsource connected to said first input terminal of said sense amplifier atone end and ground at the other end; a multiplexer having a first inputterminal, a second input terminal, and an output terminal, said firstinput terminal of said multiplexer being connected to said second inputnode, said output terminal of said multiplexer being connected to saidsecond input terminal of said sense amplifier; a first target resistorand an offset resistor connected in series between said second inputnode and said second input terminal of said multiplexer; and a secondcurrent source connected to said output terminal of said multiplexer atone end and ground at the other end, wherein said first target resistoris a variable resistor.
 2. The nonvolatile memory device of claim 1,wherein said reference resistor includes a second target resistor and abalancing resistor connected in series, said first and second targetresistors having a substantially same resistance value.
 3. Thenonvolatile memory device of claim 2, wherein said balancing resistor isa variable resistor.
 4. The nonvolatile memory device of claim 1,wherein said reference resistor includes a second target resistor, saidfirst and second target resistors have a substantially same resistancevalue.
 5. The nonvolatile memory device of claim 4, wherein said firstand second target resistors each comprise a sequence of sub-circuitsconnected in series with each sub-circuit including a transistor and aresistor connected in parallel, a resistance value of said resistordoubling in a successive sub-circuit.
 6. The nonvolatile memory deviceof claim 5, wherein said first and second target resistors each furthercomprise first and second sub-circuits, said first sub-circuit includingfirst and second magnetic tunnel junctions (MTJs) coupled in parallel,said second sub-circuit including third and fourth magnetic tunneljunctions coupled in parallel, said first sub-circuit, said secondsub-circuit, and said sequence of sub-circuits being connected inseries.
 7. The nonvolatile memory device of claim 6, wherein said first,second, third, and fourth magnetic tunnel junctions are in a lowresistance state.
 8. The nonvolatile memory device of claim 6, whereinsaid first, second, third, and fourth magnetic tunnel junctions are in ahigh resistance state.
 9. The nonvolatile memory device of claim 6,wherein said first and third magnetic tunnel junctions are in a lowresistance state and said second and fourth magnetic tunnel junctionsare in a high resistance state.
 10. The nonvolatile memory device ofclaim 1, wherein each of said one or more memory sectors includes acolumn of transistors and an array of magnetic memory cells arranged inrows and columns, each of said magnetic memory cells including an accesstransistor and a magnetic tunnel junction (MTJ) coupled in seriesbetween a respective one of a plurality of source lines and a respectiveone of a plurality of bit lines, said arrays of magnetic memory cells ofsaid one or more memory sectors including said magnetic memory cell. 11.The nonvolatile memory device of claim 10, wherein said read currentpasses through said magnetic memory cell.
 12. The nonvolatile memorydevice of claim 10, wherein said column of transistors are directlycoupled to a reference source line at one of source and drain of eachtransistor and a reference bit line at the other one of source and drainof said each transistor.
 13. The nonvolatile memory device of claim 10,wherein said reference current passes through one of said column oftransistors and bypasses said array of magnetic memory cells.
 14. Thenonvolatile memory device of claim 10, wherein said each of said one ormore memory sectors further includes at least one row of transistors.15. The nonvolatile memory device of claim 14, wherein each transistorof said at least one row of transistors is directly coupled to arespective one of said plurality of source lines at one of source anddrain of said each transistor and a respective one of said plurality ofbit lines at the other one of source and drain of said each transistor.16. The nonvolatile memory device of claim 14, wherein said calibrationcurrent passes through one transistor of said at least one row oftransistors and bypasses said array of magnetic memory cells.
 17. Anonvolatile memory device comprising one or more memory sectors and aread circuit for sensing a resistance state of a magnetic memory cell insaid one or more memory sectors, said read circuit comprising: a firstinput node through which a reference current passes; a second input nodethrough which a read current passes; a sense amplifier having first andsecond input terminals, said second input terminal connected to saidsecond input node; a reference resistor connected to said first inputnode at one end and said first input terminal of said sense amplifier atthe other end; a first current source connected to said first inputterminal of said sense amplifier at one end and ground at the other end;and a second current source connected to said second input terminal ofsaid sense amplifier at one end and ground at the other end, whereinsaid reference resistor comprises first and second sub-circuitsconnected in series, said first and second sub-circuits each includingtwo magnetic tunnel junctions (MTJs) connected in parallel, wherein saidreference resistor further comprises a sequence of sub-circuitsconnected in series with each sub-circuit including a transistor and aresistor connected in parallel, a resistance value of said resistordoubling in a successive sub-circuit of said sequence of sub-circuits,said first and second sub-circuits and said sequence of sub-circuitsbeing connected in series.
 18. A nonvolatile memory device comprisingone or more memory sectors and a read circuit for sensing a resistancestate of a magnetic memory cell in said one or more memory sectors, saidread circuit comprising: a first input node through which a referencecurrent passes; a second input node through which a read current passes;a sense amplifier having first and second input terminals, said secondinput terminal connected to said second input node; a reference resistorconnected to said first input node at one end and said first inputterminal of said sense amplifier at the other end; a first currentsource connected to said first input terminal of said sense amplifier atone end and ground at the other end; and a second current sourceconnected to said second input terminal of said sense amplifier at oneend and ground at the other end, wherein said reference resistorcomprises first and second sub-circuits connected in series, said firstand second sub-circuits each including two magnetic tunnel junctions(MTJs) connected in parallel, wherein each of said one or more memorysectors includes a column of transistors and an array of magnetic memorycells arranged in rows and columns, each of said magnetic memory cellsincluding an access transistor and a magnetic tunnel junction (MTJ)coupled in series between a respective one of a plurality of sourcelines and a respective one of a plurality of bit lines, said array ofmagnetic memory cells of said one or more memory sectors including saidmagnetic memory cell, wherein said column of transistors are directlycoupled to a reference source line at one of source and drain of eachtransistor and a reference bit line at the other one of source and drainof said each transistor.
 19. The nonvolatile memory device of claim 18,wherein said reference current passes through one of said column oftransistors and bypasses said array of magnetic memory cells.
 20. Thenonvolatile memory device of claim 18, wherein said read current passesthrough said magnetic memory cell in said one or more memory sectors.